The present invention relates to the field of reference clock signals. Specifically, the present invention relates to a high-resolution delay lock loop.
Presently, in order to maintain an efficiently operating computing system, a reference clock is utilized. In general, the reference clock is an internal timing device. Using a quartz crystal, the clock breathes life into the computing system by feeding it a constant flow of pulses. For example, a 200 MHz computing system receives 200 million pulses per second. The quartz crystal generates continuous waves, which are converted into digital pulses that are used as a signal to synchronize the operations within the electronic system. In most electronic cases, clock pulses are continuous, precisely spaced changes in voltage.
In order for all the components within the computing system to take advantage of the reference clock, the reference clock pulse is disseminated to each component within the computing system. Thus, each component is synchronized to a specific timing pattern and ordered computations may then take place. To take full advantage of the computational order within a computing system, as the clock pulse enters a specific circuit or group of circuits, a delay may be added. The delay may be used to ensure that one calculation or operation takes place before another. Additionally, the delay may be required in order for a specific component within a group of component to receive the results from another component within the same group of components.
However, once a component receives the reference clock pulse and adds a delay, the component must then return its results in phase with the original reference clock pulse. For example, a phase shift occurs if a delay is added when the reference pulse enters a component. A further delay can then be added to realign the outgoing phase with the original clock pulse. Thus, although a full 360-degree shift may have occurred within the component, the outgoing pulse is in phase with the original reference clock pulse. In many situations, the combined delay and phase alignment component are referred to as a delay lock loop (DLL).
FIG. 1 is an example of a conventional DLL. As shown in FIG. 1, the external clock pulse 101 enters the component 100 via input buffer 102. In general, input buffer 102 adds an initial delay to external clock pulse 101 due to the time required to drive the circuit. Therefore, the external clock pulse becomes a reference clock pulse 103. Reference clock pulse 103 then enters the programmable delay 104 which adds a specific delay to the already delayed reference clock pulse 103. Therefore, reference clock pulse 103 becomes an output clock pulse 105. Programmable delay 104 may be controlled by internal programming. The programmable delay is where a delay may be used to organize the order of a specific set of computations. Output clock pulse 105 then reaches the clock distribution 106 wherein it is then distributed to all places within the component or chip that it is needed.
The clock distribution 106 adds a further delay to output clock pulse 105. Upon distribution, output buffer 112 (which also maintains a delay in the output) is triggered. During the triggering of output buffer 112, output clock pulse 105 is passed through a second output buffer 122 which has the opposite value of output buffer 112 as well as an input buffer 118 which has a value opposite that of input buffer 102. Therefore, when the output clock pulse 105 reaches phase detector 108 it is now a feedback clock pulse 107. In general, both the delay due to input buffer 102 and output buffer 112 have been factored out of feedback clock pulse 107 due to the phase shifting calculations.
Phase detector 108 then detects the phase of the internal signal and tells controller 110 to add or subtract in order to regain the phase of the reference clock 103. Controller 110 then figures out how much to add or subtract in order to realign the phases of the feedback clock 107 with respect to the reference clock 103. Upon completion of the DLL circuit, the component is ready to output any resulting data 120 in a format which is in phase with external clock 101. As such, the output data 120 can easily be utilized by any other components working within the computing system on the same external clock.
When working correctly, the DLL will reduce most jitter (loss of phase synchronization) that occurs when the phase of the internal clock on output does not align with the reference clock. The reduction of jitter is accomplished by allowing the DLL to cover a range large enough to encompass most phase variations.
The problem with the DLL circuit 100 is that in order to maintain a consistent delay, which matches the reference clock phase with the least amount of jitter, there are two considerations to take into account. The first consideration is range and the second is accuracy. If the DLL is tuned for optimum range, then the accuracy will be sacrificed. Adversely, if the DLL is set for optimum accuracy, then the range is severely compromised.
If the accuracy is sacrificed, then the DLL will always maintain a certain amount of detrimental output jitter. Otherwise, if the range is compromised, then the DLL will reach a reset point more often. During a DLL reset, a large and possibly catastrophic jitter or skip may occur. In some situations, the jitter may cause complete shutdown of the system and require the user to manually reset the DLL.
A method for utilizing a delay lock loop to cover a wide delay range. In one method embodiment, the present invention receives a reference clock pulse and a feedback clock pulse. Next, in a first loop, a phase variation is adjusted between the feedback clock pulse and the reference clock pulse utilizing a coarse delay in conjunction with a first fine delay. The resulting pulse is then output to a chip delay and then sent back to the delay lock loop as a feedback clock pulse. Additionally, in a second loop, the phase variation is adjusted between said second loop and said first loop utilizing the coarse delay in conjunction with a second fine delay, wherein the second fine delay has a delay range for adjusting the phase variation which overlaps the delay range of the first fine delay of the first loop. Thus, when the phase variation moves beyond the delay range of the first fine delay of the first loop, it remains within the delay range of the second fine delay of the second loop.